Title :
A bit scalable architecture for fuzzy processors with three inputs and a flexible fuzzification unit
Author :
D´Amore, Roberto
Author_Institution :
Inst. Tecnologico de Aeronaut., Sao Jose dos Campos, Brazil
Abstract :
This paper describes an architecture of a three input one output bit scalable fuzzy processor. The synthesis is made from a VHDL description. The data path and functional units dimension are defined by a small number of parameters in the highest level entity. The knowledge base and the membership functions are stored in distinct units in the circuit description for an easy control strategy modification
Keywords :
fuzzy systems; hardware description languages; high level synthesis; microprocessor chips; pipeline processing; VHDL description; bit scalable architecture; circuit description; control strategy modification; data path; flexible fuzzification unit; functional units dimension; fuzzy processors; highest level entity; knowledge base; membership functions; Circuit synthesis; Fuzzy sets; Shape;
Conference_Titel :
Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on
Conference_Location :
Manaus
Print_ISBN :
0-7695-0843-X
DOI :
10.1109/SBCCI.2000.876004
