Polysilicon TFTs with low gate line resistance and low off-state current suitable for large area and high resolution LCDs

Author

Ono, K. ; Kimura, E. ; Suzuki, T. ; Mimura, A. ; Konishi, N. ; Miyata, K.

Author_Institution

Hitachi Ltd., Chiba, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

345

Lastpage

348

Abstract

Polysilicon TFTs (thin-film transistors) with a self-aligned platinum silicide (PtSi) gate line are studied. The PtSi was formed by reacting Pt with gate polysilicon films, and the minimum sheet resistance, 2 Omega / Square Operator , was obtained. A delay time calculation indicated that the resistance was low enough to drive a 14-in diagonal LCD (liquid-crystal display) with 780 gate lines. Boron-doped TFTs in channel polysilicon films were fabricated and compared with nondoped TFTs. Off-state current was reduced by optimizing the dose or using XeCl-lasers annealing in hydrogen-passivated TFTs. Simulations of device characteristics were carried out to understand the boron dose dependence. The effect of boron dose was seen to be strongly affected by trap state density in polysilicon films.<>

Keywords

boron; elemental semiconductors; laser beam annealing; liquid crystal displays; semiconductor technology; silicon; thin film transistors; 2 ohm; Si:B; Si:B-PtSi; TFTs; delay time calculation; device simulation; gate lines; high resolution LCDs; hydrogen-passivated TFTs; laser annealing; low gate line resistance; low off-state current; sheet resistance; trap state density; Amorphous materials; Annealing; Apertures; Boron; Delay; Hydrogen; Ice; Laboratories; Optimized production technology; Tiles;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74294

Filename

74294