Title :
A low power all-digital PLL with power optimized digitally controlled oscillator
Author :
Lee, Doo-Chan ; Kim, Kyu-Young ; Min, Young-Jae ; Kim, Kyung-Min ; Abdullah, Ammar ; Park, Jongsun ; Kim, Soo-Won
Author_Institution :
Dept. of Nano-Semicond. Eng., Korea Univ., Seoul, South Korea
Abstract :
This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm2 area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; circuit optimisation; digital control; digital phase locked loops; low-power electronics; phase locked oscillators; CMOS process; DCO power dissipation; all-digital phase locked loop; digitally controlled oscillator; low power ADPLL; low power all-digital PLL; power optimization; size 0.13 mum; CMOS integrated circuits; CMOS process; Optimization;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-9997-7
DOI :
10.1109/EDSSC.2010.5713739
