Address satisfaction for storage files with fifos or stacks during scheduling of DSP algorithms

Tight data- and timing constraints are imposed by DSP applications. Also, the target processor architecture or the synthesized circuit template conform resource constraints. Additionally, instead of registers address-limited storage files with fifos or stacks are used. Continuing previous work on register file capacity satisfaction, this paper presents a method that during scheduling handles address constraints of storage files with fifos or stacks together with timing and resource constraints