Address satisfaction for storage files with fifos or stacks during scheduling of DSP algorithms

Author

Pinto, Carlos A Alba ; van Eijk, Koen ; Mesman, Bart ; Jess, Jochen

Author_Institution

Sect. of Design Autom., Eindhoven Univ. of Technol., Netherlands

fYear

2000

fDate

2000

Firstpage

107

Lastpage

112

Abstract

Tight data- and timing constraints are imposed by DSP applications. Also, the target processor architecture or the synthesized circuit template conform resource constraints. Additionally, instead of registers address-limited storage files with fifos or stacks are used. Continuing previous work on register file capacity satisfaction, this paper presents a method that during scheduling handles address constraints of storage files with fifos or stacks together with timing and resource constraints

Keywords

computer architecture; digital signal processing chips; file organisation; processor scheduling; resource allocation; storage allocation; storage management; DSP algorithms; address constraints; bottleneck identification; fifos; register file capacity; resource constraints; scheduling; stacks; storage files; synthesized circuit template; target processor architecture; timing constraints; Application specific processors; Circuit synthesis; Design automation; Digital signal processing; Encoding; Processor scheduling; Registers; Scheduling algorithm; Timing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on

Conference_Location

Manaus

Print_ISBN

0-7695-0843-X

Type

conf

DOI

10.1109/SBCCI.2000.876016

Filename

876016