DocumentCode
252151
Title
A hybrid chaos-based pseudo-random bit generator in VHDL-AMS
Author
Melosik, Michal ; Marszalek, W.
Author_Institution
Dept. of Comput. Sci., Poznan Univ. of Technol., Poznan, Poland
fYear
2014
fDate
3-6 Aug. 2014
Firstpage
435
Lastpage
438
Abstract
A new pseudo-random bit generator with an increased level of security and possible resistance to hacker attacks is presented. The generator is based on hybrid (analog and digital) chaotic systems. We also use the VHDL-AMS language in modeling of both the chaotic systems and generator. The 0/1 test for chaos is applied to evaluate the generator´s performance.
Keywords
chaos generators; hardware description languages; mixed analogue-digital integrated circuits; random number generation; 0/1 test; VHDL-AMS language; generator performance evaluation; hacker attacks; hybrid analog and digital chaotic systems; hybrid chaos-based pseudorandom bit generator; Chaotic communication; Cryptography; Generators; Ports (Computers); Vectors; Chua circuit; Pseudo-random bit generator; VHDL-AMS; discrete chaotic map; hybrid chaotic cryptography; nonlinear circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location
College Station, TX
ISSN
1548-3746
Print_ISBN
978-1-4799-4134-6
Type
conf
DOI
10.1109/MWSCAS.2014.6908445
Filename
6908445
Link To Document