Title :
Low-power high-speed multiplier for error-tolerant application
Author :
Kyaw, Khaing Yin ; Goh, Wang Ling ; Yeo, Kiat Seng
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
In this paper, a new design concept that engaged accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed. The aim is to fulfill the need for high performance basic sequential elements with low-power dissipation which is steadily growing.
Keywords :
CMOS digital integrated circuits; high-speed integrated circuits; integrated circuit design; low-power electronics; multiplying circuits; digital IC design; error-tolerant application; low-power high-speed multiplier; power consumption; Accuracy; Educational institutions; Logic gates; CMOS technology; Multiplier; error-tolerant; high speed integrated circuits; low power; truncated;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-9997-7
DOI :
10.1109/EDSSC.2010.5713751
