A single-PLL UWB frequency synthesizer using current reusing SSB mixer

This paper presents a fast switching frequency synthesizer for a Mode-1 MB-OFDM UWB system. The proposed architecture with a new frequency plan is designed to simplify the synthesizer implementation for optimizing the system power consumption and sideband rejection ratio. This frequency generator consists of a single phase-lock-loop (PLL), a 12-phase coupled ring oscillator, tri-mode divider-by-2 circuit and a current reused single sideband mixer (SSB). The circuit is fabricated in a 0.18-μm CMOS process and it consumes 18.7mA from a 1.2V power supply. It achieves a switching time of about 3nS, and the unwanted sideband rejection ration of less than 31dBc, and the phase noise of about -103dBc/Hz@1MHz.