Robust broadband antenna array pattern synthesis technique with constrained partitioned processor

A constrained partitioned processor based broadband antenna array pattern synthesis technique with robust algorithm is presented in this paper. The constrained partitioned processor is an implementation of a broadband time domain antenna array processor using a fixed main beam steered in the look direction and a set of auxiliary beams to remove unwanted directional noise from the main beam. The weights of the auxiliary beams are constrained to block the desired signal. The processor does not use a pre-steered array and allows an array designer to specify the frequency response in an arbitrary look direction. This pattern synthesis technique is able to place multiple point nulls and broad nulls in a given sector using minimum mean power problem with quadratic constrains. This paper presents a robust pattern synthesis scheme in the presence of array imperfections which estimates the weights of the auxiliary beams require much less computation time and better performances than existing techniques.