Simulations of 3rd order voltage switched CP-PLL using a fast event switching macromodeling

The charge-pump phase-locked loop (CP-PLL) has gained an essential place in the wide area of the radio frequency (RF) communication and industrial electronics. Since it is a combination of analog and digital elements, it enhances the complexity to study the transient behavior of an arbitrary ordered CP-PLL using any general feedback system concept. Concerning the PLL circuit, particularity that operating with voltage switched charge pump (VSCP) supplements the peculiarity arising in the form of non-constant pump current. Whereas its characterization in transient time off-locking and on-locking region remains critical due to its unbalanced pumping characteristics. The linear models are valid for small phase errors in the locked state. However, transistor level models are very near to the real design but are constrained with time-inefficiency and computer resource consumption. In this paper, the transient behavior of the 3^rd order VSCP-PLL is investigated using an ultra-fast and resource efficient event-driven (ED) macro-modeling technique. Due to its inherent competency, the off-locking behavior of the system can easily be characterized. Related to the VSCP-PLL architecture, the ED model is simulated and some features are highlighted using piece-wise linear and non-linear VCO. Moreover, the work is extended to compare its performance with an equivalent PLL operating with a current switched charge-pump (CSCP) for a constant and ramp function of the reference frequency.