Title :
Advanced multi-high-operation-voltage I/O device design for 32nm gate-first HiK MG technology
Author :
Wu, Xusheng ; Hu, Y. ; Kusunoki, N. ; Yang, Z.J. ; Yang, G. ; Teh, Y. ; Kirshnan, R. ; Krishnan, Sridhar ; Shepard, J. ; Han, S. ; Lee, Y. ; Arnaud, F. ; Sherony, M. ; Sudijono, J. ; Steegen, A.
Abstract :
This paper presents the advanced I/O device design for 32 nm Hi-K Metal Gate technology with multi-high operation voltages. Process optimization work is done on the I/O composite gate dielectric stack to improve TDDB Vmax. By using advanced junction engineering, 3.3 V device Isubmax is reduce by 30-40% without Ion degradation based on TCAD simulation guideline. At the same time, 2.5 V device drive current and DIBL performance are maintained without degradations. Reliability stress testing result further confirms the inline electrical result with same trend. 3.3V I/O TDDB, HCI, and BTI results are reported.
Keywords :
CMOS integrated circuits; field effect transistors; high-k dielectric thin films; integrated circuit design; integrated circuit reliability; integrated circuit testing; BTI; CMOS techniques; DIBL performance; HCI; I/O TDDB; I/O composite gate dielectric stack; NFET; TCAD simulation guideline; advanced junction engineering; advanced multihigh-operation-voltage I/O device design; complementary metal oxide semiconductor techniques; device drive current; gate-first HiK MG technology; high-K-metal gate technology; ion degradation; process optimization; reliability stress testing; size 32 nm; time-dependent dielectric breakdown; voltage 2.5 V; voltage 3.3 V; Human computer interaction; Junctions; Logic gates; Optimization; Performance evaluation; Reliability; Transistors; HCI; HiK Metal Gate; I/O; Junction Engineering; Reliability; TDDB;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-9997-7
DOI :
10.1109/EDSSC.2010.5713769
