Energy-efficient processing through adaptation and resiliency

Summary form only given. Today´s SoC devices are often constrained by both performance and power requirements. New software capabilities and usage models demand more processing power than ever before, however the increased integration requires advanced power management techniques. Process scaling, which makes this all possible, also leads to increased susceptibility to variations static process variations as well as dynamic environmental variations in voltage, temperature, and transistor aging. Design of an energy-efficient SoC requires innovations at both circuits and architecture level in tolerating variations and enabling low-voltage operation. The paper discusses the role that variations play in the performance and power of a processing block. It describe how adaptive techniques can be used to reduce the impact of variations and enable low-voltage, lowpower operation of both the logic and memory blocks. It also describes resilient circuit techniques that incorporate error-detection and correction circuits into the processor core. These techniques allow correct operation even in the presence of large dynamic variations, resulting in an energy-efficient design that naturally adapts to its operating environment.