Efficient equalization hardware architecture for SC-FDMA systems without cyclic prefix

Single carrier frequency domain multiple access (SC-FDMA) system achieves better spectral efficiency when cyclic prefix (CP) is not transmitted. However, the chained turbo equalization (CHATUE) algorithm, an equalizer required to both equalize the multipath fading effect and cancel the inter-block interference of SC-FDMA without CP, requires high computational complexity due to the non-circulant structure of the past and the future interference matrices. This paper proposes efficient hardware architecture based on systolic architecture for practical implementation. The main idea is to minimize the number of required processing elements by utilizing efficient resources sharing method while exploiting concurrency of the processing. A new computation method using masking matrices is introduced to obtain interference matrix from its corresponding circulant channel matrix. The results with fixed point computation show that the computational complexity can be significantly reduced up to 96% for practical implementation without significant degradation in bit-error-rate (BER) performances.