• DocumentCode
    2522337
  • Title

    Ultra low energy standard cell design optimization for performance and placement algorithm

  • Author

    Amarchinta, S. ; Kudithipudi, D.

  • Author_Institution
    Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
  • fYear
    2010
  • fDate
    15-18 Aug. 2010
  • Firstpage
    509
  • Lastpage
    517
  • Abstract
    Most medical implantable devices and wearable electronics have critical battery life requirements. Such devices will fundamentally benefit from ultra low voltage or subthreshold operation of circuits, leading to longer battery life. In this work, we focus on designing a subthreshold standard cell library and improving their performance using charge boosters. The performance-enhanced standard cell library is implemented on ISCAS´85 benchmark circuits and a 10 times improvement in frequency with an overhead of approximately 2 times in the energy-delay product is observed. We also propose a placement methodology to integrate the enhanced cells using Critical Path Method (CPM) algorithm to minimize the overhead in energy consumption. A 50 % reduction in energy was achieved with implementation of CPM.
  • Keywords
    cellular arrays; critical path analysis; low-power electronics; optimisation; portable instruments; ISCAS85 benchmark circuits; charge boosting; critical battery life requirements; critical path method; design optimization; medical implantable devices; subthreshold standard cell library; ultra low energy standard cell; wearable electronics; Analytical models; Boosting; Computational modeling; Logic gates; MOSFETs; ILP; charge boosting; optimization; standard cell library; substrate biasing; subthreshold;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Green Computing Conference, 2010 International
  • Conference_Location
    Chicago, IL
  • Print_ISBN
    978-1-4244-7612-1
  • Type

    conf

  • DOI
    10.1109/GREENCOMP.2010.5598273
  • Filename
    5598273