Title :
Optimization of a dot product accelerator
Author_Institution :
Cisco Syst., San Jose, CA, USA
Abstract :
Vector dot product is an important computation which needs hardware accelerators. We present an optimized accelerator chip that has larger capacity than our prior designs. This design can compute product for 10000 component vectors within 1000 clock cycles, with average being 80 cycles. Our design has superior speed compared to other accelerators.
Keywords :
clocks; integrated circuit design; microprocessor chips; optimisation; clock cycles; component vectors; design; dot product accelerator; hardware accelerators; optimization; optimized accelerator chip; vector dot product; Clocks; Computer aided manufacturing; Computer architecture; Hardware; Optimization; Testing; Vectors; Dot product coprocessor; parallelization;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908491
