Reducing instruction TLB´s leakage power consumption for embedded processors

This paper presents a leakage efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage structure which stores the recent address-translation information, the TLB access frequency can be drastically decreased and the instruction TLB can be turned into the low leakage mode with the dual voltage supply technique. Based on such a design philosophy, three different implementation policies are proposed. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.