• DocumentCode
    2522478
  • Title

    Latency tolerant branch predictors

  • Author

    Santana, Oliverio J. ; Ramirez, Alex ; Valero, Mateo

  • Author_Institution
    Departament d´´Architectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
  • fYear
    2003
  • fDate
    37819
  • Firstpage
    30
  • Lastpage
    39
  • Abstract
    The access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex recovery mechanism to discard the wrong speculative work based on overridden predictions. In this paper, we show that stream and trace predictors, which use long basic prediction units, can tolerate access latency without needing overriding, thus reducing fetch engine complexity. We show that both the stream fetch engine and the trace cache architecture not using overriding outperform other efficient fetch engines, such as an EV8-like fetch architecture or the FTB fetch engine, even when they do use overriding.
  • Keywords
    cache storage; instruction sets; parallel architectures; program compilers; system recovery; access latency; fetch architecture; fetch engine complexity; fetch engine design; latency tolerant branch predictors; prediction overriding; recovery mechanism; stream fetch engine; stream predictors; trace cache architecture; trace predictors; Bandwidth; Buildings; Cache storage; Clocks; Delay; Engines; Frequency; Parallel processing; Performance analysis; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
  • ISSN
    1537-3223
  • Print_ISBN
    0-7695-2019-7
  • Type

    conf

  • DOI
    10.1109/IWIA.2003.1262780
  • Filename
    1262780