Analysis and modeling of advanced PIM architecture design tradeoffs

Processor in memory or PIM architecture offers dramatic improvements in performance for computations that exhibit poor locality. PIM provides high memory bandwidth and low access latency on-chip. Future PIMs may incorporate more nodes, multithreading for local latency hiding, and lightweight message-driven computing to tolerate system-wide latencies. This paper describes a series of queuing simulation experiments and analytical studies using statistical steady-state parametric models to evaluate the design tradeoff space of these advanced concepts in PIM. The results show a range of improvements as a function of structural and operational parameters.