Bridging the gap between complex software paradigms and power-efficient parallel architectures

Achieving extreme-scale computing requires power-efficiency of the computing elements. Power efficiency is usually achieved by cutting transistor budget from hardware structures that exploit locality such as caches and replacing them with software-managed local-store to maintain performance; it can also require removing hardware structures that exploit instruction level parallelism that is not well expressed in software, such as out-of-order execution units - leaving support only for vector execution units. Power efficiency generally leads to complicating software development. Heterogeneous systems provide a tradeoff that combines complex processor cores with power-efficient accelerators to handle multiple code types. Manually migrating code to accelerator-based architectures has proved the performance and power efficiency benefits of using these architectures, but at the cost of reducing productivity. In the absence of a convincing automated process, migrating codes to these architectures or developing new codes proves to be so time-consuming and cumbersome that most computational scientists are reluctant to pursue, especially with the uncertainty about the future of these architectures. The success of powerefficient architectures depends on how well we automate the code generation process. In this paper, we present a model that efficiently exploit accelerator-based systems while being amenable to automatic translation from conventional software codes. We show that the performance achieved with this execution model is comparable to hand-optimized code for multiple case studies.