DocumentCode
2522772
Title
Analysis and optimization of HV ESD protection
Author
Wang, S.J. ; Yao, F. ; Qin, B. ; Wang, Xiongfei ; Zhao, H. ; Fang, Q. ; Lin, L. ; Wang, Aiping ; Chen, H.Y.
Author_Institution
CitrusCom Semicond., Inc., China
fYear
2010
fDate
15-17 Dec. 2010
Firstpage
1
Lastpage
4
Abstract
Adequate ESD protection is a new design challenge for HV electronics. This paper presents design, failure analysis and optimization of a HVggLDMOS ESD protection structure in a HV BCD process. Theoretical analysis involving Kirk effect and mixed-mode ESD simulation-design technique were used to analyze experimental results and to optimize the HV ESD protection structure.
Keywords
BIMOS integrated circuits; MOSFET; circuit simulation; electrostatic discharge; failure analysis; high-voltage engineering; mixed analogue-digital integrated circuits; power integrated circuits; HV BCD process; HV electronics; HV grounded-gate LDMOS; HVggLDMOS ESD protection; Kirk effect; failure analysis; high-voltage electronics; mixed-mode ESD simulation-design technique; Analytical models; Electrostatic discharge; Heating; Logic gates; Variable speed drives; ESD; HV; Kirk Effect; LDMOS;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location
Hong Kong
Print_ISBN
978-1-4244-9997-7
Type
conf
DOI
10.1109/EDSSC.2010.5714031
Filename
5714031
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