Title :
DLL-based pulse-width modulation digital-to-analog converter for continuous-time sigma delta modulators
Author :
Zong-Yi Chen ; Chung-Chih Hung
Author_Institution :
Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, the DLL-based pulse-width modulation (PWM) digital-to-analog converter (DAC) is proposed to convert the output of multi-bit quantizer to a single-bit pulse-width modulated signal in the modified continuous-time sigma-delta modulators (CT-SDMs) with improved signal transfer function (STF). The DLL-based PWM DAC is more robust to clock jitter and excess loop delay (ELD) effects than conventional multi-bit DAC and other PWM DAC with similar speed and power requirements of the integrators in CT-SDMs. Furthermore, the proposed PWM DAC is based on inherently linear single-bit DAC, so the dynamic-element matching (DEM) techniques, which increase the circuit complexity and power consumption to compensate the mismatch of unit elements in the multi-bit DAC, can be removed in CT-SDMs.
Keywords :
PWM power convertors; circuit complexity; delay lock loops; digital-analogue conversion; jitter; power consumption; sigma-delta modulation; transfer functions; CT-SDMs; DEM techniques; DLL-based pulse-width modulation digital-to-analog converter; ELD effects; PWM-DAC; STF; circuit complexity; clock jitter; continuous-time sigma delta modulators; dynamic-element matching techniques; excess loop delay effects; improved signal transfer function; linear single-bit DAC; mismatch compensation; multibit quantizer; power consumption; single-bit pulse-width modulated signal; unit elements; Clocks; Delays; Jitter; Optical signal processing; Pulse width modulation; Shape;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908525