DocumentCode :
2523292
Title :
Hardware/software interface for multi-dimensional processor arrays
Author :
Darte, Alain ; Derrien, Steven ; Risset, Tanguy
Author_Institution :
CNRS, ENS-Lyon, Lyon, France
fYear :
2005
fDate :
23-25 July 2005
Firstpage :
28
Lastpage :
35
Abstract :
On most recent systems on chip, the performance bottleneck is the on-chip communication medium, bus or network. Multimedia applications require a large communication bandwidth between the processor and graphic hardware accelerators, hence an efficient communication scheme using burst mode is mandatory. In the context of data-flow hardware accelerators, we approach this problem as a classical resource-constrained problem. We explain how to use recent optimization techniques so as to define a conflict-free schedule of input/output for multi-dimensional processor arrays (e.g. 2D grids). This schedule is static and allows us to perform further optimizations such as grouping successive data in packets to operate in burst mode. We also present an effective VHDL implementation on FPGA and compare our approach to a run-time congestion resolution showing important gains in hardware area.
Keywords :
field programmable gate arrays; hardware description languages; logic CAD; multiprocessing systems; system-on-chip; 2D grid; FPGA; VHDL; data-flow hardware accelerator; graphic hardware accelerator; hardware-software interface; multidimensional processor array; multimedia application; on-chip communication; optimization technique; resource-constrained problem; run-time congestion resolution; systems-on-chip; Application software; Bandwidth; Context; Field programmable gate arrays; Graphics; Hardware; Network-on-a-chip; Processor scheduling; Runtime; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on
ISSN :
2160-0511
Print_ISBN :
0-7695-2407-9
Type :
conf
DOI :
10.1109/ASAP.2005.38
Filename :
1540362
Link To Document :
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