12 bits, 40MS/s, low power pipelined SAR ADC

Author

Lazarjan, Vahid Khojasteh ; Hajsadeghi, Khosrow

Author_Institution

Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

841

Lastpage

844

Abstract

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); low-power electronics; power consumption; CMOS technology; ENOB; FOM; comparator architecture; effective number of bits; high speed sampling rate; low power pipelined SAR ADC; power 4.5 mW; power consumption; size 0.18 mum; system level modifications; voltage 1.2 V; word length 11.04 bit; word length 12 bit; CMOS integrated circuits; Capacitance; Capacitors; Digital circuits; Power demand; Timing; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908546

Filename

6908546