Robust subthreshold 7T-SRAM cell for low-power applications

In this paper, a novel 7T-SRAM cell for ultra-low power applications is proposed. The proposed SRAM cell is fully functional at subthreshold voltages down to VDD_min=200mV. In this technique, separate read/write bitlines and wordlines are used that makes read and write operation independent. The 7T-SRAM cell proposed in this paper, improves static read noise margin, write margin, and write time by 2.2X, 27%, and 6% in comparison to the standard 6T-SRAM cell. The 7T-SRAM cell proposed in this paper, improves write margin of the conventional 7T-SRAM cell, as well. The proposed 7T-SRAM cell is designed in 65nm CMOS technology.