• DocumentCode
    2523817
  • Title

    An image processor for digital film

  • Author

    Lucas, Amilcar Do Carmo ; Ernst, Rolf

  • Author_Institution
    Inst. of Comput. & Commun. Network Eng., Tech. Univ., Braunschweig, Germany
  • fYear
    2005
  • fDate
    23-25 July 2005
  • Firstpage
    219
  • Lastpage
    224
  • Abstract
    This paper presents an FPGA based hardware architecture, named FlexWAFE, for high resolution, high troughput real-time digital film processing. Complex algorithms require several hundred arithmetic operations per pixel which is beyond the scope of current DSP processors. To simplify programming and yet achieve high clock rates, the architecture combines component configuration with weak programmability. It alleviates the memory bottleneck by an efficient use of internal memory blocks and a multi-stream SDRAM memory scheduler with tightly bounded latency. Several examples of a discrete wavelet transform and a complex noise reducer demonstrate the architecture efficiency.
  • Keywords
    DRAM chips; discrete wavelet transforms; field programmable gate arrays; image processing; memory architecture; DSP processor; FPGA; FlexWAFE; arithmetic operation; complex noise reducer; digital film processing; discrete wavelet transform; hardware architecture; image processor; multistream SDRAM memory scheduling; Arithmetic; Clocks; Delay; Digital signal processing; Discrete wavelet transforms; Field programmable gate arrays; Hardware; Noise reduction; Processor scheduling; SDRAM; FPGA; digital .lm; recon.gurable; stream-based architechture; weak-programing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on
  • ISSN
    2160-0511
  • Print_ISBN
    0-7695-2407-9
  • Type

    conf

  • DOI
    10.1109/ASAP.2005.13
  • Filename
    1540389