DocumentCode
2523870
Title
The NUMAchine multiprocessor
Author
Grindley, R. ; Abdelrahman, T. ; Brown, S. ; Caranci, S. ; DeVries, D. ; Gamsa, B. ; Grbic, A. ; Gusat, M. ; Ho, R. ; Krieger, O. ; Lemieux, G. ; Loveless, K. ; Manjikian, N. ; McHardy, P. ; Srbljic, S. ; Stumm, M. ; Vranesic, Z. ; Zilic, Z.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear
2000
fDate
2000
Firstpage
487
Lastpage
496
Abstract
Small-scale multiprocessors are becoming increasingly economical and common, whereas larger multiprocessors continue to have higher per-node costs. The NUMAchine multiprocessor project seeks to make large-scale multiprocessors more economical while maintaining high performance by exploring architectural and hardware features for low-cost, modular multiprocessors. To demonstrate our approach, we have implemented a prototype system that is scalable to 128 processors. An efficient directory-based cache coherence protocol exploits our hierarchical ring-based interconnect and supports sequential consistency. This paper documents the design choices and the resulting performance of the system using both simulation results and measurements on the prototype hardware
Keywords
multiprocessing systems; parallel architectures; NUMAchine multiprocessor; directory-based cache coherence protocol; large-scale multiprocessors; multiprocessors; performance; prototype hardware; ring-based interconnect; sequential consistency; Costs; Hardware; Integrated circuit interconnections; Large-scale systems; Maintenance engineering; Multicast protocols; Prototypes; Scalability; Switches; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 2000. Proceedings. 2000 International Conference on
Conference_Location
Toronto, Ont.
ISSN
0190-3918
Print_ISBN
0-7695-0768-9
Type
conf
DOI
10.1109/ICPP.2000.876165
Filename
876165
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