Title :
A programmable DSP architecture for wireless communication systems
Author :
Kamalizad, Amir ; Tabrizi, Nozar ; Bagherzadeh, Nader ; Hatanaka, Akira
Author_Institution :
Dept. of EECS, UC Irvine, CA, USA
Abstract :
Programmable solutions for fast mobile communication systems are attracting ever-growing attention due to different and also evolving communication standards. They overcome the shortcomings of ASIC design, by allowing multimode operation, and general-purpose processors by exploiting the inherent data level parallelism in the application. MaRS, a macro-pipelined reconfigurable system, is a domain specific programmable parallel DSP architecture, aimed at harnessing the inherent parallelism in such applications. In this paper, we present the MaRS architecture along with the latest modifications and algorithms that are mapped onto it. We have mapped an IEEE 802.11a WLAN transmitter including a parallel FFT and soft decision Viterbi decoder on MaRS. Our simulation results show that the performance achieved on MaRS meets the stringent timing constraints of the IEEE 802.11a baseband transceiver at its highest rate, with 20% slack, leaving a playground for system level power optimization. Finally, we have mapped the EEMBC telecom suite on MaRS to evaluate and compare our architecture with existing architectures.
Keywords :
IEEE standards; Viterbi decoding; digital signal processing chips; mobile communication; parallel architectures; pipeline processing; power consumption; IEEE 802.11a WLAN transmitter; data level parallelism; macropipelined reconfigurable system; mobile communication system; parallel FFT; power optimization; programmable DSP architecture; programmable parallel DSP architecture; soft decision Viterbi decoder; wireless communication system; Application specific integrated circuits; Communication standards; Decoding; Digital signal processing; Mars; Mobile communication; Transmitters; Viterbi algorithm; Wireless LAN; Wireless communication;
Conference_Titel :
Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on
Print_ISBN :
0-7695-2407-9
DOI :
10.1109/ASAP.2005.9