• DocumentCode
    2524052
  • Title

    Consequences of port restrictions on testing two-port memories

  • Author

    Hamdioui, S. ; van de Goor, A.J.

  • Author_Institution
    Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
  • fYear
    1998
  • fDate
    18-23 Oct 1998
  • Firstpage
    63
  • Lastpage
    72
  • Abstract
    Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible fault models, the tests for single-port and two-port memories, as well as the test strategy. This paper presents a test strategy for two-port memories and covers the consequences of the port restrictions (read-only or write-only ports)
  • Keywords
    fault diagnosis; integrated circuit testing; multiport networks; read-only storage; fault models; port restrictions; read-only ports; single-port tests; two-port memories; two-port tests; write-only ports; Conductivity; Frequency conversion; Logic arrays; Logic devices; Low voltage; Random access memory; Read-write memory; Resource description framework; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1998. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-5093-6
  • Type

    conf

  • DOI
    10.1109/TEST.1998.743138
  • Filename
    743138
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2524052