Reducing interconnection resource overhead in nano-scale FPGAs through MVL signal systems

In nano-architectures, transistor counts place extreme demands on interconnection resources. The chronic problem of interconnect area versus device area becomes more acute than it currently is. Even with multilayering of conductors there may still be attenuation and propagation delay issues which at the extremes of nano-architecture severely limit performance. When reconfigurable devices such as field programmable gate arrays (FPGAs) are considered the issue of interconnection resources becomes even more acute due to the inherent redundancy already apparent in existing devices. The authors propose the use of a multiple valued signal system to increase functional density whilst reducing the interconnection resource overhead in FPGA based nano-architectures.