A new framework for generating optimal March tests for memory arrays

Author

Zarrineh, Kamran ; Upadhyaya, Shambhu J. ; Chakravarty, Sreejit

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

73

Lastpage

82

Abstract

Given a set of memory array faults the problem of computing an optimal March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory army fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compute the optimal March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented

Keywords

automatic test pattern generation; electronic engineering computing; fault diagnosis; integrated circuit testing; integrated memory circuits; optimisation; complete MAF sequences; complete primitive sequences; functional fault; memory array faults; multiple cell memory array fault; optimal March tests; optimisation; primitive memory fault; test automatic generation; Automatic testing; Circuit faults; Coupling circuits; Decoding; Digital systems; Educational institutions; Fault detection; Logic arrays; Logic testing; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743139

Filename

743139