DocumentCode :
2524109
Title :
Delay test of chip I/Os using LSSD boundary scan
Author :
Gillis, Pamela ; Woytowich, Francis ; McCauley, Kevin ; Baur, Ulrich
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fYear :
1998
fDate :
18-23 Oct 1998
Firstpage :
83
Lastpage :
90
Abstract :
This paper describes a novel design-for-test (DFT) concept for I/O delay testing while contacting very few pads, using boundary scan and new test-generation software. In production testing of the IBM System/390 Generation 3TM and several ASIC chips, these patterns uncovered unique manufacturing defects
Keywords :
application specific integrated circuits; automatic test software; boundary scan testing; delays; design for testability; production testing; ASIC chips; DFT; I/O delay testing; IBM System/390 Generation; LSSD boundary scan; boundary scan; chip I/O; design-for-test; level sensitive scan design; manufacturing defects; production testing; test-generation software; Automatic testing; Circuit testing; Delay effects; Driver circuits; Latches; Logic testing; Packaging; Performance evaluation; Software testing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-5093-6
Type :
conf
DOI :
10.1109/TEST.1998.743140
Filename :
743140
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2524109
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