RF channelizer architectures using Iterative Downconversion for concurrent or fast-switching spectrum analysis

We propose an RF channelizer architecture that uses the concept of 3-way Iterative Down-Conversion (IDC) to channelize a wideband incident spectrum while only using a fixed LO synthesizer. The proposed architecture can realize a concurrent channelizer that can analyze channels simultaneously, or a fast-switching channelizer that can analyze channels sequentially but with very short switching times between channels. We present an RF channelizer demonstrator prototype that was fabricated in a 65nm CMOS process. It implements a partially-concurrent architecture with the ability to concurrently down-convert a subset of channels while being able to switch very quickly between the non-concurrent channels. It splits an input spectrum of 0.6GHz-9GHz into 7 channels each of 1.2GHz bandwidth. Channelizer performance depends on the selected operation mode. The measured channel switching duration can be as fast as 8ns, and is always under 1μs. The chip occupies an area of 2mm × 1mm and consumes an average power of 435mW while offering a dynamic range between 58dB to 63dB based on noise and linearity performance.