A New On-Chip Interconnection Network for System-on-Chip

With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of system-on-chip (SoC) design. Network-on-chip (NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely accepted by academe and industry. Focusing on decreasing node degrees, reducing links and reusing router nodes, a regular NoC architecture, named generalized Petersen (GP(2m,1)) graph interconnection network, is proposed. The topology of GP(2m,1) is simple, symmetric and scalable in architecture, and it is 3-regular plane graph with 4 m nodes. The nodes of GP(2m,1) adopt Johnson coding scheme that can make the design of routing algorithms simple and efficient. The GP(2m,1) was compared with ring and 2D mesh by simulating and analysing, both under uniform load and under more realistic load assumptions in the several network size scenarios. The results show that the GP(2m,1) topology is a good trade-off between performance and cost, and it is a better NoC topology when there are not too many network nodes.