DocumentCode :
2524272
Title :
Scheduling DAGs for Fixed-point DSP Processors by Using Worm Partitions
Author :
Hong, Jinpyo ; Ramanujam, J.
Author_Institution :
Sch. of Internet-Media, Korea Univ. of Technol. & Educ., Cheonan
fYear :
2008
fDate :
29-31 July 2008
Firstpage :
567
Lastpage :
574
Abstract :
This paper concerns a code generation for directed acyclic graphs (DAGs). The set of edges that connect consecutively scheduled operations along with the nodes that correspond to the consecutively scheduled operations constitutes a worm. We propose an algorithm to construct a partitioning of a DAG into a collection of worms. This is done by finding the longest worm at the moment and maintaining the legality of worm partitioning. We characterize a legality of worm partitioning by introducing a simple set notation and proving its property. Based on that notation and its property, we prove that our algorithm correctly works. We also show that our algorithm works even in a DAG which contains interleaved sharing. Experimental results on several DAGS show that our technique generates worm partitioning of DAGs with small cardinality.
Keywords :
digital signal processing chips; directed graphs; fixed point arithmetic; logic partitioning; program compilers; scheduling; DAG partitioning; DAG scheduling; code generation; consecutively scheduled operations; directed acyclic graphs; fixed-point DSP processors; interleaved sharing; worm partitioning; Computer worms; Digital signal processing; Embedded system; Law; Legal factors; Optimal scheduling; Partitioning algorithms; Processor scheduling; Registers; Signal processing algorithms; Embedded Systems; Scheduling; Worm Partition;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Software and Systems, 2008. ICESS '08. International Conference on
Conference_Location :
Sichuan
Print_ISBN :
978-0-7695-3287-5
Type :
conf
DOI :
10.1109/ICESS.2008.89
Filename :
4595611
Link To Document :
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