A new BiCMOS/CMOS gate comparison/design methodology and supply voltage scaling model

Author

Raje, P. ; Saraswat, K. ; Cham, K.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

433

Lastpage

436

Abstract

A novel BiCMOS/CMOS gate comparison methodology is proposed and demonstrated with fabrication in a BiCMOS technology. The concept of the sizing plane is presented as a general framework for BiCMOS gate design interpretation of performance comparison results, and extraction of the true technology dependent component in gate performance comparisons. An analytical model is derived to predict BiCMOS gate delay at reduced supply voltage, and it is verified by experimental data. The model is used to present gate design and device scaling guidelines for optimized operation under reduced supply.<>

Keywords

BIMOS integrated circuits; delays; integrated circuit technology; logic gates; BiCMOS gate delay; BiCMOS gate design; BiCMOS/CMOS gate comparison/design methodology; analytical model; device scaling guidelines; gate performance comparisons; optimized operation; sizing plane; supply voltage scaling model; Analytical models; BiCMOS integrated circuits; CMOS technology; Data mining; Delay; Design methodology; Design optimization; Fabrication; Guidelines; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74315

Filename

74315