DocumentCode
2524296
Title
A novel embedded SRAM technology with 10-/spl mu/m/sup 2/ full-CMOS cells for 0.25-/spl mu/m logic devices
Author
Izawa, T. ; Katsube, M. ; Yokoyama, Y. ; Hashimoto, K. ; Kawamura, E. ; Shimizu, A. ; Takagi, H. ; Inoue, F. ; Shimizu, H. ; Furumochi, K. ; Goto, H. ; Kawamura, Sadao ; Watanabe, K. ; Aoyama, K.
Author_Institution
LSI Process Dev. Div., Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
1994
fDate
11-14 Dec. 1994
Firstpage
941
Lastpage
943
Abstract
Am embedded SRAM technology for 0.25 /spl mu/m logic LSIs is described. The key of the technology is a single-level local interconnect with a TiN film. The local interconnect wires driver and load´s drains, and input gate of the counterpart inverter besides. We achieved 10-/spl mu/m/sup 2/ full CMOS SRAM cells by the technology.<>
Keywords
CMOS integrated circuits; SRAM chips; driver circuits; integrated logic circuits; invertors; 0.25 mum; 10 mum; TiN film; driver drains; embedded SRAM technology; full CMOS SRAM cells; full-CMOS cells; input gate; inverter; load drains; local interconnect wires; logic LSIs; logic devices; single-level local interconnect; Doping; Inverters; Logic devices; MOS devices; Oxidation; Propagation delay; Random access memory; Tin; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-2111-1
Type
conf
DOI
10.1109/IEDM.1994.383256
Filename
383256
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