The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing

In the block ciphers, though the operation is quite complex, there are a lot of similar characteristics including arithmetic unit, operation width, parallel data and ordinal implement. It is very suitable for designing ASIP (application specific instruction set processor) targeted at block ciphers. In this thesis, a reconfigurable processor architecture is proposed, At the mean time, in order to improve instruction level parallelism. This thesis put forward the instruction bundle structure based on VLIW architecture, which supports word and sub-word parallel processing. As to the design of cipher arithmetic units, we adopt a specific design which is reconfigurable, so as to make the architecture have instruction level reconfigurable function. Besides, In order to solve the bottleneck of storage and access, this thesis adopt clustered technology to design two separated register files to storage data and subkey. Furthermore, this scheme reduces energy and clock cycles. A number of algorithms were implemented successfully on the processor. The prototype is realized using Alterapsilas FPGA. Synthesis, placement and routing of processor have accomplished under 0.18 mum CMOS technology through design complier tool. Compared with other ASIP targeted at block cipher, the results prove that processor can achieve relatively high performance in block cipher algorithms processing.