Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

Author

Chang, Jonathan T Y ; Tseng, Chao- Wen ; Li, Chien-Mo James ; Purtell, Mike ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

184

Lastpage

193

Abstract

This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) defects at very low voltage. Multiple-detect single stuck fault test sets have high transition fault coverage. Most dies with TIC or non-TIC defects were close to gross failures or next to the wafer periphery

Keywords

combinational circuits; failure analysis; fault diagnosis; integrated circuit testing; large scale integration; logic testing; combinational defects; experimental test chip; fault coverage; multiple-detect single stuck fault test; pattern-dependent failures; repeatability; retest; test ordering; test sets; test timing; timing-dependent failures; wafer periphery; Circuit faults; Circuit testing; Clocks; Failure analysis; Packaging; Pattern analysis; Probes; System testing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743151

Filename

743151