Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec

A high performance and silicon efficient hardware architecture for binary arithmetic coding (BAC) acceleration is presented and its application to entropy coding in the context of the H.264 video compressor standard described. The proposed hardware architecture remains bit compatible with the software implementation used in the H.264 ITU standard. The renormalization sequence that maintains the state variables in the appropriate range has been rewritten in order to enable a data independent throughput in hardware of 1 symbol per clock cycle. The instruction set extensions required to be implemented as part of the ISA of a controlling RISC are proposed. Finally, ASIC and FPGA implementations are obtained and the performance and complexity compared with recent implementations of the well-known MQ-coder reported.