Synthesis of carry select adder in 65 nm FPGA

Due to rapidly growing system-on-chip industry, not only the faster units but also smaller area and less power has become a major design constraint for VLSI community. Further, demand for high speed is continuously increasing. In processors, most commonly used arithmetic operation is the addition operation. It is the adder delay that determines the maximum frequency of operation of the chip. Different topologies have been put forward, each providing trade-off between different performance parameters and as such no design is considered as superior. Carry select adder is considered to be best in terms of speed and provide compromise between ripple carry adder and carry look-ahead adder, but to a lesser extent at the cost of its area. The goal of this work is to synthesize and optimize the delay, area and Power-Delay Product (PDP) of carry select adder in 65 nm technology using FPGA´s. This work proposes a new highspeed, low area design methodology for carry select adder. Basic cell of this proposed topology consists of an XOR gate, one inverter and two multiplexers. Further this proposed logic has been optimized in order to reduce the delay by making use of universal NAND gates. As a result of this area, delay and hence PDP has been reduced to larger extent. Glitches have also eliminated by proper selection of topology. Further, the result of the proposed-optimized carry select adder has been verified analytically by the method of Logical Effort.