A 0.4-/spl mu/m/sup 2/ self-aligned contactless memory cell technology suitable for 256-Mbit flash memories

Author

Kato, M. ; Adachi, T. ; Tanaka, T. ; Sato, A. ; Kobayashi, T. ; Sudo, Y. ; Morimoto, T. ; Kume, H. ; Nishida, T. ; Kimura, K.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

921

Lastpage

923

Abstract

This paper describes advanced self-aligned contactless memory-cell technology with sector erase and programming operations for a single power supply 256-Mbit flash memory. Using new self-aligned field-isolation technology and a deep punch-through stopper while minimizing the thermal budget of memory-cell fabrication process, 0.40-/spl mu/m/sup 2/ cells based on 0.25-/spl mu/m CMOS processes are fabricated.<>

Keywords

CMOS memory circuits; EPROM; integrated circuit technology; isolation technology; 0.25 micron; 256 Mbit; 3 V; CMOS processes; deep punch-through stopper; field-isolation technology; flash memories; memory cell fabrication process; sector erase; sector programming; self-aligned contactless memory cell; self-aligned memory cell technology; single power supply; Boron; Fabrication; Flash memory; Isolation technology; Laboratories; Nonvolatile memory; Power engineering and energy; Threshold voltage; Ultra large scale integration; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383263

Filename

383263