Title :
Improving Priority Lot Cycle Times
Author_Institution :
AMD Saxony LLC & Co. KG, Dresden
Abstract :
ISMI member companies defined two master goals for the 300 mm prime initiative (see [2]): 50% cycle time reduction and 30% cost reduction. Combining these conflicting goals into a holistic approach represents a major challenge. This paper outlines how this goal can be targeted for priority lots. Though only a small share of WIP is priority lots, the benefit of short priority lot cycle time can be very persuading and the impact on overall costs very significant.
Keywords :
cost reduction; integrated circuit manufacture; lot sizing; wafer-scale integration; IC manufacturers; ISMI member company; Semiconductor Fab; WIP; cost reduction; lot cycle times; Context; Costs; Degradation; Integrated circuit modeling; Measurement; Production facilities; Qualifications; Semiconductor device manufacture;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference, 2007. ASMC 2007. IEEE/SEMI
Conference_Location :
Stresa
Print_ISBN :
1-4244-0652-8
DOI :
10.1109/ASMC.2007.4595694