• DocumentCode
    252480
  • Title

    Advanced High K/Metal SOI technologies for 32nm and beyond

  • Author

    Horstmann, M.

  • Author_Institution
    GLOBALFOUNDRIES Dresden, Dresden, Germany
  • fYear
    2014
  • fDate
    6-9 Oct. 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Within the semiconductor industry, pure leading edge foundries serve a special mission by delivering state-of-the-art competitive logic performance with a strong focus on system-on-chip (SoC) solutions. Therefore they have to support a broad portfolio of different technology options on each node. GLOBALFOUNDRIES is an industry leader by representing this particular business model and has a long experience in leading-edge semiconductor manufacturing and technology capabilities, particular on silicon on insulator (SOI) based high performance microprocessors (table 1). To achieve a “high performance per watt” figure of merit, technology elements like partial depleted (PD) -SOI, strained-Si, ultra low K BEOL and HKMG were needed together with an efficient multiple core- and power-efficient design. Those technology elements were developed and optimized for multiple generations beginning from an 180nm down to the 28nm technology node which runs currently in high volume production. In particular the 28nm node should remain for a long time at the sweet spot in the Foundry Industry for yield, performance and cost reasons. This node will be the foundation to add technology features like Flash, HV, MEMS etc. but also will enable a quick productization of new innovations like fully depleted extreme thin (ET) planer SOI devices with back bias options (BB), reducing power consumption even further.
  • Keywords
    low-power electronics; microprocessor chips; silicon-on-insulator; system-on-chip; back bias options; fully depleted extreme thin planer SOI devices; high k-metal SOI technologies; high performance microprocessors; power consumption; size 28 nm; size 32 nm; system-on-chip; FinFETs; Foundries; Logic gates; Metals; Performance evaluation; Silicon-on-insulator; Technological innovation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
  • Conference_Location
    Millbrae, CA
  • Type

    conf

  • DOI
    10.1109/S3S.2014.7028183
  • Filename
    7028183