High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique

Author

Nguyen, P. ; Barraud, S. ; Koyama, M. ; Casse, M. ; Andrieu, F. ; Tabone, C. ; Glowacki, F. ; Hartmann, J.-M. ; Maffini-Alvaro, V. ; Rouchon, D. ; Bernier, N. ; Lafond, D. ; Samson, M.-P. ; Allain, F. ; Vizioz, C. ; Delprat, D. ; Nguyen, B.-Y. ; Mazure, C

Author_Institution

LETI, CEA, Grenoble, France

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

Ω-gate nanowires (NW) P-FETs on compressively-strained-SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (L_G=15nm and W_NW=25nm) with an outstanding I_ON current (I_ON=860μA/μm at I_OFF=140nA/μm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si_0.8Ge_0.2-channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for L_G=30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at L_G=15nm.

Keywords

Ge-Si alloys; electrostatics; field effect transistors; germanium; hole mobility; nanowires; semiconductor-insulator boundaries; substrates; cSGOI channel; cSGOI substrate; channel transistor; compressive strain; compressively-strained silicon germanium-on-insulator substrate; electrostatics immunity; field effect transistor; gate length; germanium enrichment technique; high mobility Ω-gate nanowire PFET; hole mobility; ultrascaled P-FET NW; Logic gates; Silicon; Silicon germanium; Strain; Substrates; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028187

Filename

7028187