DocumentCode :
2524875
Title :
The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory
Author :
Muramatsu, S. ; Kubota, T. ; Nishio, N. ; Shirai, H. ; Matsuo, M. ; Kodama, N. ; Horikawa, M. ; Saito, S. ; Arai, K. ; Okazawa, T.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
fYear :
1994
fDate :
11-14 Dec. 1994
Firstpage :
847
Lastpage :
850
Abstract :
Clear evidence is presented that the floating gate poly-Si grain size dominates flash memory erase characteristics. Smaller grain size shows a narrower erase distribution. Thus conventional scaling theories should be modified to include that grain size must be shrunk proportional to the cell size. A process technology breakthrough will have to be achieved to form smaller size grains because 16 M will be the maximum capacity using current process technology with this new theory. It is also shown how 64 M flash memories can be achieved without such a technology breakthrough.<>
Keywords :
EPROM; elemental semiconductors; grain size; integrated circuit modelling; integrated memory circuits; silicon; 16 Mbit; 64 Mbit; Si; erase distribution; flash memory; floating gate; memory erase characteristics; modified scaling principles; over-erase problem; oxide valley model; poly-Si grain size; Annealing; Circuits; Flash memory; Grain size; Laboratories; National electric code; Nonvolatile memory; Size control; Temperature dependence; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-2111-1
Type :
conf
DOI :
10.1109/IEDM.1994.383280
Filename :
383280
Link To Document :
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