A half-micron ferroelectric memory cell technology with stacked capacitor structure

Author

Onishi, S. ; Hamada, K. ; Ishihara, K. ; Ito, Y. ; Yokoyama, S. ; Kudo, J. ; Sakiyama, Kazuo

Author_Institution

VLSI Dev. Lab., Sharp Corp., Nara, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

843

Lastpage

846

Abstract

A half-micron ferroelectric technology applicable to mega-bit non-volatile memories is reported. 10.5 /spl mu/m/sup 2/ 1transistor/1capacitor cell with a stacked capacitor structure is successfully achieved using planarization by CMP (chemical mechanical polishing), dry etching at the high temperature and TiO/sub 2/ diffusion barrier technologies. The capacitance above 50 fF is obtained at the size of 1.5 /spl mu/m/spl times/1.5 /spl mu/m, which satisfies the primary requirements for 4M NVDRAM operation.<>

Keywords

DRAM chips; capacitor storage; capacitors; etching; ferroelectric capacitors; ferroelectric devices; polishing; 1.5 mum; 4M NVDRAM operation; 50 fF; TiO/sub 2/; TiO/sub 2/ diffusion barrier technologies; capacitance; chemical mechanical polishing; dry etching; half-micron ferroelectric memory cell technology; igh temperature; mega-bit non-volatile memories; planarization; stacked capacitor structure; transistor/capacitor cell; Annealing; Capacitors; Contact resistance; Crystallization; Degradation; Dry etching; Electrodes; Fabrication; Ferroelectric materials; Scanning probe microscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383281

Filename

383281