Abstract :
With widespread acceptance of the IEEE 1149.1 standard, structured interconnect testing has become extremely important at the MCM, PWB and system levels. In the conventional paradigm, an interconnect topology model of the system under test is extracted from design information. From this model, interconnect test patterns can be generated by means of well understood algorithms. We demonstrate a new approach whereby the interconnect topology model is extracted by directly probing a hardware prototype of the system under test. This Golden Model can then be used to generate interconnect tests for other systems whose interconnect topology matches that of the prototype. Algorithms for this Golden Model extraction are presented and analyzed, empirical results are given, and the benefits and drawbacks of the approach are discussed
Keywords :
IEEE standards; automatic test pattern generation; boundary scan testing; built-in self test; integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; multichip modules; Golden Model extraction; IEEE 1149.1 standard; boundary scan; interconnect models generation; interconnect test pattern generation; interconnect topology model; prototype hardware; pseudocode; splitting algorithm; structured interconnect testing; system under test; Algorithm design and analysis; Circuit topology; Data mining; Design automation; Electronic equipment testing; Hardware; Prototypes; Surface-mount technology; System testing; Test pattern generators;
