Energy efficiency benefits of subthreshold-optimized transistors for digital logic

Using a simulation-based approach, the energy efficiency of the MIT Lincoln Laboratory xLP process was benchmarked against two commercial low power process technologies for a ~40,000 gate DES enryption circuit to demonstrate the benefits of subthreshold-optimized transistors for minimum energy circuit design. Because the transistors are tuned for low voltage operation, the xLP process performs best relative to other technologies at subthreshold supply voltages, where most circuits achieve their minimum energy point. With 90nm feature sizes, the xLP process at showed a 57% percent energy efficiency improvement vs. IBM 90nm technology and a 9% energy efficiency improvement vs. IBM 65 nm. Scaling the xLP process to 65 nm should provide further energy efficiency benefit.