Vertically-integrated package

A packaging concept has been developed to optimize system integration for electronic designs that contain VLSI semiconductors requiring a large quantity of passive-component support. The concept was realized by designing an inverted-cavity, leadless ceramic chip carrier that uses two surfaces for component attachment. Semiconductors and similar devices that require environmental protection are mounted and hermetically sealed in the lower, recessed cavity. Metallized vias pass vertically from the cavity base through multiple interconnect layers to bonding pads on the chip carrier´s top surface for mounting resistor and capacitor chips. By combining active and passive components within the same structure by using two surfaces, packaging density is greatly increased over that of comparable chip and wire hybrid designs. Furthermore, this concept provides for full burn-in and electrical characterization of active and passive components prior to substrate assembly.<>