Synthesis of clock gating logic through factored form matching

Clock gating is typically dictated by designers in register transfer level (RTL). Automatic synthesis of clock gating in gate level has been less explored, but is certainly more convenient to designers; it can also complement RTL clock gating by extracting additional gating conditions. The key problem in gate-level clock gating synthesis is to implement gating conditions with minimum amount of additional logic. In this paper, we aim to utilize the existing combinational logic as much as possible. This is done by extracting a factored form (modeled by a factoring tree) of each gating condition, and try to cover the tree by factoring trees of existing combinational logic; the corresponding process is named factored form matching. Experiments demonstrate that the proposed matching achieves 25% reduction in the number of gates to implement gating conditions; this can be compared to prior method using Boolean division, which achieves 10% reduction.