Title :
Design and implementation of the “G2” PowerPCTM 603e-embedded microprocessor core
Author :
Hunter, Craig ; Gaither, Justin
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
New and emerging demands in the embedded market has precipitated in the development of the “G2” PowerPC 603e microprocessor into a reusable hard core. The demands and requirements of an embedded core microprocessor require significant changes in the physical design, verification and test strategies. Reuse and standardization in design data and test data present new challenges for an existing family of microprocessors
Keywords :
automatic test pattern generation; boundary scan testing; design for testability; embedded systems; formal verification; hardware-software codesign; integrated circuit testing; microprocessor chips; reduced instruction set computing; ATPG model; G2 PowerPC 603e microprocessor; HyperMOS3; JTAG port; boundary scan circuitry; core integration; data reuse; data standardization; debug processor interface; design; embedded microprocessor core; implementation; pattern data format; power bussing; reusable hard core; superscalar processor; test strategies; verification strategies; Circuits; Clocks; Design optimization; Logic devices; Microprocessors; Power generation; Routing; Testing; Time to market; Wire;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743188
